1. Field of the Invention
This invention relates to a computational adder overflow indicating method and an apparatus of the same, and more particularly, to a method and an apparatus for indicating the computational adder overflow status of bit-variable data employing a pipelining adder.
2. Description of Pertinent Technology
To date, an adder in integrated form is a very basic and important element for arithmetic operation in electronic devices and computers. The overflow signal generated from the adder is also important as a reference signal for many control applications and for judging whether the adding result is correct or not. For example, for a 8-bit adder, if the adding result is 256, the data output by the adder would be 00000001. This result is apparently wrong because the adder is in overflow status. The overflow signal can be used to indicate the error or to correct the adding result. Usually, a register is used to store a carry bit which indicates the overflow status of the adder. Generally, if overflow signals of each multiple-bit data are to be output respectively, a plurality of adders must be used to respectively calculate the plurality of multiple-bit data in which the numbers and bit-lengths of the adders are predetermined corresponding to the numbers and bit-lengths of the multiple-bit data. As shown in FIG. 1, there are N multiple-bit data needed to be respectively calculated. Hence, the architecture has to comprise N adders 1a to 1d and N overflow indicating devices 2a to 2d. Each adder has a different bit-length corresponding to the data being calculated. For example, the adder 1a is a 3-bit adder, the adder 1b is a 6-bit adder, the adder 1c is a 8-bit adder and the adder 1d is a 12-bit adder. The adders 1a to 1d are respectively employed to process the four kind of data, i.e., 3-bit data DA1, 6-bit data DB1, 8-bit data DC1 and 12-bit data DD1. The input data DA1, DB1, DC1 and DD1 are correspondingly added with the output (i.e., DA2, DB2, DC2 and DD2, respectively) of the adders. And the overflow indicating devices 2a to 2d are respectively employed to indicate the overflow status of the adders 1a to 1d. However, these types of architectures are too complex and expensive because of the need for a large number of adders. Moreover, these types of structures appear wasteful when it is desired to merely output the overflow signal but not the adding result.